Creation of vias with optimized profile for 3-D through silicon interconnects (TSV)

Plasma Processes and Polymers

Volumn 6, Issue SUPPL. 1, 2009, Pages

  Richter, Karola ^a   Viehweger, Kay ^a   He, Jian ^a   Bartha, Johann Wolfgang ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

Deep reactive ion etch of silicon (DRIE); Positive etch profile; Tapered side walls; Through silicon interconnects; Through silicon vias (TSV)

Indexed keywords

DEEP REACTIVE ION ETCH; DEEP REACTIVE ION ETCH OF SILICON (DRIE); ETCH PROFILE; POSITIVE ETCH PROFILE; SIDE WALLS; THROUGH SILICON VIAS;

ASPECT RATIO; INNOVATION; OPTIMIZATION; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICES; THREE DIMENSIONAL;

IONS;

EID: 77954942423     PISSN: 16128850     EISSN: 16128869     Source Type: Journal    
DOI: 10.1002/ppap.200930501     Document Type: Conference Paper

References (9)

1. B. Swinnen, W. Ruythooren, P. De Moor, L. Bogaerts, L. Carbonell, K. De Munck, B. Eyckens, S. Stoukatch, D. Sabuncuoglu Tezcan, Z. Tökei, J. Vaes, J. Van Aelst, E. Beyne, IEDM Tech. Digest. 2006, 1-4.
2. D. Thomas, Semiconductor International, 2/1/2007.
3. B. Kim, Semiconductor International, 2/1/2007.
4. F. Lärmer, A. Schilp, German Patent DE 4241045 C1, 1994.
5. J. Bhardwaj, H. Ashraf, SPIE 1995, 2639, 224.
6. K. Richter, D. Fischer, DE 103 18 568 A1, 2003.
7. K. Richter, D. Fischer, WO 2004/093162 A2. 2004.
8. K. Richter, G. Zschätzsch, DE 10 2006 043 389 A1, 2006.
9. K. Richter, G. Zschätzsch, J.-W. Bartha, Plasma Process. Polym. 2007, 882-886.