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Volumn , Issue , 2010, Pages 105-108

Performing floating-point accumulation on a modern FPGA in single and double precision

Author keywords

[No Author keywords available]

Indexed keywords

DOUBLE PRECISION; FPGA DEVICES; HIGH OPERATING FREQUENCY;

EID: 77954309015     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2010.24     Document Type: Conference Paper
Times cited : (16)

References (9)
  • 1
    • 34247161863 scopus 로고    scopus 로고
    • A low-cost real-time hardware-in-the-loop testing approach of power electronics controls
    • April
    • B. Lu, X. Wu, H. Figueroa, and A. Monti, "A low-cost real-time hardware-in-the-loop testing approach of power electronics controls," IEEE Transactions on Industrial Electronics, vol. 54, no. 2, pp. 919-931, April 2007.
    • (2007) IEEE Transactions on Industrial Electronics , vol.54 , Issue.2 , pp. 919-931
    • Lu, B.1    Wu, X.2    Figueroa, H.3    Monti, A.4
  • 2
    • 34547133729 scopus 로고    scopus 로고
    • FPGA design methodology for industrial control systems- A review
    • Aug.
    • E. Monmasson and M. Cirstea, "FPGA design methodology for industrial control systems - a review," IEEE Transactions on Industrial Electronics, vol. 54, no. 4, pp. 1824-1842, Aug. 2007.
    • (2007) IEEE Transactions on Industrial Electronics , vol.54 , Issue.4 , pp. 1824-1842
    • Monmasson, E.1    Cirstea, M.2
  • 5
    • 42549129981 scopus 로고    scopus 로고
    • Control system with high-speed and real-time communication links
    • April
    • T. Li and Y. Fujimoto, "Control system with high-speed and real-time communication links," IEEE Transactions on Industrial Electronics, vol. 55, no. 4, pp. 1548-1557, April 2008.
    • (2008) IEEE Transactions on Industrial Electronics , vol.55 , Issue.4 , pp. 1548-1557
    • Li, T.1    Fujimoto, Y.2
  • 7
    • 78650423490 scopus 로고    scopus 로고
    • An FPGA-specific approach to floating-point accumulation and sum-of-products
    • IEEE
    • F. de Dinechin, B. Pasca, O. Creţ, and R. Tudoran, "An FPGA-specific approach to floating-point accumulation and sum-of-products," in Field-Programmable Technologies. IEEE, 2008, pp. 33-40.
    • (2008) Field-Programmable Technologies , pp. 33-40
    • De Dinechin, F.1    Pasca, B.2    Creţ, O.3    Tudoran, R.4
  • 8
    • 0033733825 scopus 로고    scopus 로고
    • Accelerating pipelined integer and floating-point accumulations in configurable hardware with delayed addition techniques
    • Mar
    • Z. Luo and M. Martonosi, "Accelerating pipelined integer and floating-point accumulations in configurable hardware with delayed addition techniques," IEEE Transactions on Computers, vol. 49, no. 3, pp. 208-218, Mar 2000.
    • (2000) IEEE Transactions on Computers , vol.49 , Issue.3 , pp. 208-218
    • Luo, Z.1    Martonosi, M.2
  • 9
    • 33749527748 scopus 로고    scopus 로고
    • A 6.2-gflops floating-point multiply-accumulator with conditional normalization
    • Oct.
    • S. Vangal, Y. Hoskote, N. Borkar, and A. Alvandpour, "A 6.2-gflops floating-point multiply-accumulator with conditional normalization," IEEE Journal of Solid-State Circuits, vol. 41, no. 10, pp. 2314-2323, Oct. 2006.
    • (2006) IEEE Journal of Solid-State Circuits , vol.41 , Issue.10 , pp. 2314-2323
    • Vangal, S.1    Hoskote, Y.2    Borkar, N.3    Alvandpour, A.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.