Memory in processor: A novel design paradigm for supercomputing architectures

Proceedings of the 2003 Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '03

Volumn , Issue , 2003, Pages 19-26

  Venkateswaran, N ^a   Krishnan, Aditya ^b   Kumar, S Niranjan ^b   Shriraman, Arrvindh ^b   Sridharan, Srinivas ^b,c  

^a WAran Research FoundaTion   (India)

^b WARF   (India)

^c UNIVERSITY OF NOTRE DAME   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

128-BIT DATA; CLUSTER-BASED; CONVENTIONAL APPROACH; DEVICE CHIPS; FUNCTIONAL UNITS; GRAPH ALGORITHMS; LOGIC-MEMORY ARCHITECTURES; MATRIX; NOVEL DESIGN; PROCESSOR-IN-MEMORY; UNIPROCESSORS;

COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; NANOTECHNOLOGY;

STATIC RANDOM ACCESS STORAGE;

EID: 77953590541     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1152923.1024298     Document Type: Conference Paper

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