A programmer's view of performance monitoring in the PowerPC microprocessor

IBM Journal of Research and Development

Volumn 41, Issue 3, 1997, Pages 345-356

  Levine, F E ^{a,b,c,d,e,f,g}   Roth, C P ^h,i,j,k  

^a IBM MICROELECTRONICS   (United States)

^b TUFTS UNIVERSITY   (United States)

^c PURDUE UNIVERSITY   (United States)

^d Loral Corp   (United States)

^e Cape Kennedy   (United States)

^f PowerPC Syst Arch Department   (United States)

^g PM API   (United States)

^h IBM   (United States)

ⁱ TEXAS A AND M UNIVERSITY   (United States)

^j UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^k IBM RISC Syst/6000 Proc Des Group ^*

more..

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SOFTWARE SELECTION AND EVALUATION; USER INTERFACES;

APPLICATION PROGRAMMING INTERFACE (API); PERFORMANCE MONITOR (PM);

MICROPROCESSOR CHIPS;

EID: 0031144860     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.413.0345     Document Type: Article

References (10)

1. IBM Microelectronics Division and Motorola Inc., PowerPC 604 RISC Microprocessor User's Manual, Chapter 9: Performance Monitor, 1994, pp. 9-1-9-11.
2. E. Welbon, C. Chan-Nui, D. Shippy, and D. Hicks, "POWER2 Performance Monitor," IBM RISC System/6000 Technology: Volume II, IBM Corporation, 1994, pp. 55-62.
3. C. Roth, F. Levine, and E. Welbon, "Performance Monitoring on the PowerPC 604 Microprocessor," Proceedings of the 1995 IEEE International Conference on Computer Design: VLSI in Computers & Processors, October 3, 1995, pp. 212-215.
4. ™ 604 Performance Monitor for OLTP Workloads," Proceedings of COMPCON '96, the Forty-First IEEE Computer Society International Conference: Technologies for the Information Superhighway, February 25-28, 1996, pp. 111-116.
5. C. Roth and F. Levine, "PowerPC Performance Monitor Evolution," Proceedings of the 1997 IEEE International Performance, Computing and Communications Conference, February 5-7, 1997, pp. 331-336.
6. H. Dwyer, R. Heisch, F. Levine, and E. Welbon, "Technique for Speculatively Sampling Performance Parameters," IBM Tech. Disclosure Bull. 37, No. 9, 589-592 (September 1994).
7. ™Architecture: A Specification for a New Family of RISC Processors, Second Edition, Morgan Kaufman Publishers, Inc., San Francisco, 1994, pp. 351-357, 479-481.
8. F. Levine, "Generic Performance Interface Approach," IBM Tech. Disclosure Bull. 39, No. 8, 65-68 (August 1996).
9. F. Levine and W. Starke, "Generic Performance Monitor Interface Events List Encoding," IBM Tech. Disclosure Bull. 39, No. 8, 251-254 (August 1996).
10. F. Levine, "Decoding of a Specific Performance Monitor Encoded Request to a Generic Format," IBM Tech. Disclosure Bull. 39, No. 8, 169-171 (August 1996).