Experimental analysis model of an active cooling method for 3D-ICs utilizing a multidimensional configured thermoelectric

Annual IEEE Semiconductor Thermal Measurement and Management Symposium

Volumn , Issue , 2010, Pages 55-58

  Phan, Huy N ^a   Agonafer, Dereje ^a  

^a University of Texas at Arlington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3D ARCHITECTURES; 3D SYSTEMS; ACTIVE COOLING; CATASTROPHIC FAILURES; EXPERIMENTAL ANALYSIS; EXPERIMENTAL MODELS; HEAT DISSIPATION; HIGH-POWER; LOW-POWER MEMORY; NONUNIFORM; PACKING DENSITY; POWER ARCHITECTURES; REAL ESTATE; THERMAL MANAGEMENT;

COMPUTER ARCHITECTURE; TEMPERATURE CONTROL; THERMAL VARIABLES MEASUREMENT;

THREE DIMENSIONAL;

EID: 77952624026     PISSN: 10652221     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/STHERM.2010.5444315     Document Type: Conference Paper

References (5)

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2. R. Hon, S. Lee, S. Zhang, C. Wong, "Multi-Stack Flip Chip 3D Packaging with Copper Plated Through-Silicon Vertical Interconnection", Electronic Packaging Technology Conference, IEEE, pp 384-389, 2005
3. F. Schindler-Saefkow, O. Wittler, D. May, B. Michel, "Thermal management in a 3D-PCB-Package with water cooling", IEEE, p.107-110, 2006.
4. S. Novotny, et al., "Active temperature gradient reducer," U.S Patent No. 6,581,388, 2003.
5. G. Chrysler, et al., "Thermoelectric cooling assembly with optimized fin structure for improved thermal performance and manufacturability," U.S Patent No. 5,456,081, 1995.