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Volumn 48, Issue 3 PART 3, 2009, Pages

Stacking of single-grain thin-film transistors

(6) Mofrad, Mohammad Reza Tajari a Derakhshandeh, Jaber a Ishihara, Ryoichi a Baiano, Alessandro a Van der Cingel, Johan a Beenakker, Kees a

a DELFT UNIVERSITY OF TECHNOLOGY (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BOTTOM LAYERS; FINITE ELEMENT METHOD SIMULATION; HIGH-SPEED INTEGRATED CIRCUITS; INTERCONNECT DELAY; LASER CRYSTALLIZATION; LOW TEMPERATURES; METAL OXIDE SEMICONDUCTOR; MONOLITHICALLY INTEGRATED; N-CHANNEL; P-CHANNEL MOS; SILICON LAYER; SINGLE-GRAIN THIN-FILM TRANSISTOR; THREE-DIMENSIONAL (3D); TWO LAYERS; VERTICAL STACKING;

DELAY CIRCUITS; FINITE ELEMENT METHOD; MONOLITHIC INTEGRATED CIRCUITS; SEMICONDUCTING ORGANIC COMPOUNDS;

THIN FILM TRANSISTORS;

EID: 77952484095 PISSN: 00214922 EISSN: 13474065 Source Type: Journal
DOI: 10.1143/JJAP.48.03B015 Document Type: Article

Times cited : (11)

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