Reliability improvement in planar MONOS cell for 20nm-node multi-level NAND flash memory and beyond

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Sakamoto, Wataru ^a   Yaegashi, Toshitake ^a   Okamura, Takayuki ^a   Toba, Takayuki ^a   Komiya, Ken ^a   Sakuma, Kiwamu ^a   Matsunaga, Yasuhiko ^a   Ishibashi, Yutaka ^a   Nagashima, Hidenobu ^a   Sugi, Motoki ^a   Kawada, Nobuhito ^a   Umemura, Masashi ^a   Kondo, Masaki ^a   Izumida, Takashi ^a   Aoki, Nobutoshi ^a   Watanabe, Toshiharu ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BURIED CHARGES; CELL SPACES; CELL STRUCTURE; CYCLING STRESS; IMPROVED RELIABILITY; MULTI-LEVEL; NAND FLASH MEMORY; PROGRAM/ERASE; RELIABILITY IMPROVEMENT; RETENTION CHARACTERISTICS;

ELECTRON DEVICES;

FLASH MEMORY;

EID: 77952407919     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424211     Document Type: Conference Paper

References (2)

1. Siyoung Choi, Seung Jae Baik and Joo-Tae Moon, "Band Engineered Charge Trap NAND Flash with sub-40nm Process Technologies," IEDM Tech. Dig., pp.925-928, 2008.
2. Toshitake Yaegashi et al., "20nm-node Planar MONOS Cell Technology for Multi-level NAND Flash Memory," Symp. on VLSI Technology, Tech. Dig., pp.190-191, 2009.