20nm-node planer MONOS cell technology for multi-level NAND flash memory

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2009, Pages 190-191

  Yaegashi, T ^a   Okamura, T ^a   Sakamoto, W ^a   Matsunaga, Y ^a   Toba, T ^a   Sakuma, K ^a   Gomikawa, K ^a   Komiya, K ^a   Nagashima, H ^a   Akahori, H ^a   Sekine, K ^a   Kai, T ^a   Ozawa, Y ^a   Sugi, M ^a   Watanabe, S ^a   Narita, K ^a   Umemura, M ^a   Kutsukake, H ^a   Sakuma, M ^a   Maekawa, H ^a   Ishibashi, Y ^a   Sugimae, K ^a   Koyama, H ^a   Izumida, T ^a   Kondo, M ^a   Aoki, N ^a   Watanabe, T ^a   more..

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CELL TECHNOLOGY; EXCELLENT PERFORMANCE; MULTI-LEVEL; NAND FLASH MEMORY;

NAND CIRCUITS; PLANERS; TECHNOLOGY;

FLASH MEMORY;

EID: 71049115156     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. K. Kim, and J.Choi, NVSMW, pp.9 (2006)
2. D. Kwak et al., Symp. On VLSI Tech., pp.12 (2007)
3. H. T. Lue et al., Symp. On VLSI Tech., pp.116 (2008)
4. J. S. Sim et al., NVSMW, pp.110 (2007)