A 45nm 37.3GOPS/W heterogeneous multi-core SoC

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 100-101

  Yuyama, Yoichi ^a   Ito, Masayuki ^a   Kiyoshige, Yoshikazu ^a   Nitta, Yusuke ^a   Matsui, Shigezumi ^a   Nishii, Osamu ^a   Hasegawa, Atsushi ^a   Ishikawa, Makoto ^b   Yamada, Tetsuya ^b   Miyakoshi, Junichi ^b   Terada, Koichi ^b   Nojiri, Tohru ^b   Satoh, Makoto ^b   Mizuno, Hiroyuki ^b   Uchiyama, Kunio ^b   Wada, Yasutaka ^c   Kimura, Keiji ^c   Kasahara, Hironori ^c   Maejima, Hideo ^d  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b HITACHI LTD   (Japan)

^c WASEDA UNIVERSITY   (Japan)

^d TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC PARALLELIZATION; COARSE GRAINS; CONSUMER ELECTRONICS APPLICATIONS; CPU CORES; DATA FLOW; DATABASE SEARCHES; DIGITAL TV SYSTEMS; DYNAMICALLY RECONFIGURABLE PROCESSORS; EXECUTION TIME; FACE DETECTION; HETEROGENEOUS MULTICORE; IP NETWORKS; LOW FREQUENCY; LOW POWER; MATRIX; MULTI CORE; POWER CONSUMPTION; SCIENTIFIC APPLICATIONS; SOUND PROCESSING; THEORETICAL PERFORMANCE; TV SYSTEMS; VIDEO DATA; VIDEO PROCESSING UNIT;

CONSUMER ELECTRONICS; DATA TRANSFER; DIGITAL TELEVISION; IMAGE RECOGNITION; INFORMATION RETRIEVAL; OPTICAL FLOWS; PROGRAM COMPILERS; PROGRAMMABLE LOGIC CONTROLLERS; SEARCH ENGINES; VIDEO RECORDING;

MICROPROCESSOR CHIPS;

EID: 77952207417     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5434031     Document Type: Conference Paper

References (7)

1. K. Iwata, et al., "A 342mW Mobile Application Processor with Full-HD Multi- Standard Video Codec", ISSCC Dig. Tech. Papers, pp.158-159, Feb. 2009.
2. H. Shikano, et al., "Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding", IEEE Journal of Solid-State Circuits, pp.902-910, Apr. 2008.
3. H. Kondo, et al., "Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications", IEEE Journal of Solid-State Circuits, pp.2251-2259, Aug. 2009.
4. M. Ito, et al., "An 8640 MIPS SoC with Independent Power-off Control of 8 CPUs and 8 RAMs by an Automatic Parallelizing Compiler", ISSCC Dig. Tech. Papers, pp.90-91, Feb. 2008.
5. Bell, S, et al., "TILE64 - Processor: A 64-Core SoC with Mesh Interconnect", ISSCC Dig. Tech. Papers, pp.88-89, Feb. 2008.
6. O. Takahashi, et al., "Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI", ISSCC Dig. Tech. Papers, pp.86-87, Feb. 2008.
7. H. M. Waidyasooriya, et al., "Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays", Proc. of ERSA, pp.291-294, Jul. 2009.