A 0.511 GHz CMOS low noise amplifier using dual-channel shunt technique

IEEE Microwave and Wireless Components Letters

Volumn 20, Issue 5, 2010, Pages 280-282

  Lai, Qiang Tao ^a   Mao, Jun Fa ^a  

^a SHANGHAI JIAO TONG UNIVERSITY   (China)

Author keywords

CMOS; Dual channel shunt; Low noise amplifier (LNA); Ultra wideband (UWB)

Indexed keywords

3 DB BANDWIDTH; CHIP SIZES; CMOS LOW NOISE AMPLIFIERS; CMOS PROCESSS; DUAL CHANNEL; DUAL-CHANNEL SHUNT; FLAT-GAIN; INDUCTIVE-SERIES PEAKING; INPUT RETURN LOSS; MAXIMUM POWER GAIN; POWER CONSUMPTION; RESISTIVE FEEDBACK; WIDE-BAND INPUT IMPEDANCE;

BROADBAND AMPLIFIERS; CMOS INTEGRATED CIRCUITS; ELECTRIC IMPEDANCE; ULTRA-WIDEBAND (UWB);

LOW NOISE AMPLIFIERS;

EID: 77952010282     PISSN: 15311309     EISSN: None     Source Type: Journal    
DOI: 10.1109/LMWC.2010.2045592     Document Type: Article

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