Erratum: Analytical expressions for high-frequency VLSI interconnect impedance extraction in the presence of a multilayer conductive substrate (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2009) 28:7 (1047-1060))

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 29, Issue 5, 2010, Pages 849-

  Srivastava, Navin ^a   Xu, Chuan ^b   Suaya, Roberto ^a   Banerjee, Kaustav ^b  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 77951691279     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2047753     Document Type: Erratum

References (1)

1. N. Srivastava, R. Suaya, and K. Banerjee, “Analytical expressions for high-frequency VLSI interconnect impedance extraction in the presence of a multilayer conductive substrate,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 28, no. 7, pp. 1047 1060, Jul. 2009.