FPGA realization of the neural speed estimator for the drive system with elastic coupling

IECON Proceedings (Industrial Electronics Conference)

Volumn , Issue , 2009, Pages 2831-2836

  Kaminski, Marcin ^a   Orlowska Kowalska, Teresa ^a  

^a WROCLAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN PROCESS; DRIVE SYSTEMS; ELASTIC COUPLING; ELASTIC JOINTS; ELECTRICAL DRIVE SYSTEMS; INPUT VECTOR; INTERNAL STRUCTURE; MACHINE SPEED; MOMENT OF INERTIA; NEURAL NETWORK STRUCTURES; PARALLEL SIGNAL PROCESSING; PARAMETERS IDENTIFICATION; RE-CONFIGURABLE; SPEED ESTIMATOR; TRAINING AND TESTING;

COUPLINGS; ESTIMATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INDUCTION MOTORS; INDUSTRIAL ELECTRONICS; SIGNAL PROCESSING;

NEURAL NETWORKS;

EID: 77951568189     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IECON.2009.5415403     Document Type: Conference Paper

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