Computation of a nonlinear squashing function in digital neural networks

Proceedings - 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS

Volumn , Issue , 2008, Pages 18-21

  Havel, Vladimír ^a   Vlcek, Karel ^a  

^a VSB TECHNICAL UNIVERSITY OF OSTRAVA   (Czech Republic)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; COMPUTER NETWORKS; ELECTRON TUBES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); NETWORKS (CIRCUITS); TABLE LOOKUP;

ELECTRONIC CIRCUITS;

NEURAL NETWORKS;

EID: 51049085333     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DDECS.2008.4538748     Document Type: Conference Paper

References (22)

1. Holt, J.L., Hwang, J-N. "Finite precision error analysis of neural network hardware implementations", IEEE Trans. Comput., 42, (3), pp. 281-290, 1993.
2. Moerland, P.D., Fiesler, E. "Neural network adaptations to hardware implementations", in Fiesler E and Beale R, editors, Handbook of Neural Computation, E1.2:1-13. Institute of Physics Publishing and Oxford University Publishing, New York, 1997.
3. Holt, J.L, Baker, T.E. "Backpropagation simulations using limited precision calculations", International Joint Conference on Neural Networks (IJCNN-91), vol. 2, July 1991, pp. 121-126.
4. Nichols, K., Moussa, M., Areibi, S. "Feasibility of Floating-Point Arithmetic in FPGA based Artificial Neural Networks", in Proceedings of the 15th International Conference on Computer Applications in Industry and Engineering, San Diego, California, 2002.
5. Hecht-Nielsen, R.: Neurocomputing, Addison Wesley, 1991.
6. Gordon, R. "A Calculated Look at Fixed-Point Arithmetic", Embedded.com, 1998, URL http://www.embedded.com/98/9804fe2.htm.
7. Ayala, J. L., López-Vallejo, M. "Data-Quantization Policies for Power and Area Minimization of Hardware Neural Networks", Design of Circuits and Integrated Systems Conference, Santander (Spain), November 2002.
8. Goldberg, D. "What every computer scientist should know about floating-point arithmetic", ACM Computing Surveys, March 1991.
9. Moerland, P., Fiesler, E., "Neural Network adaptations to hardware Implementations", in Fiesler E and Beale R, editors, Handbook of Neural Computation, E1.2:1-13. Institute of Physics Publishing and Oxford University Publishing, New York, 1997.
10. Nichols, K., A Reconfigurable computing architecturefor implementing artificial neural networks on FPGA. Thesis. University of Guelph, 2003.
11. Axelsson J., "Hardware/Software Partitioning of Real-Time Systems", IEEE Colloquium on Partitioning in Hardware-Software Codesigns, February 13, pp. 5/1-5/8, 1995.
12. Tommiska, M.T., "Efficient digital implementation of the sigmoid function for reprogrammable logic", Computers and Digital Techniques, IEE Proceedings - Volume 150, Issue 6, 17 Nov. 2003 Page(s): 403-411.
13. Myers, D.J., Hutchinson, R.A. "Efficient implementation of piecewise linear activation function for digital VLSI neural networks", Electron. Lett., 25, (24), pp. 1662-1663, 1989.
14. Alippi, C., Storti-Gajani, G. "Simple approximation of sigmoidal functions: realistic design of digital neural networks capable of learning", Proc. IEEE Int. Symp. on Circuits and Systems, Singapore, 11-14 June 1991, pp. 1505-1508. "",
15. Amin, H., Curtis, K.M., Hayes-Gill, B.R. "Piecewise linear approximation applied to nonlinear function of a neural network", IEE Proc. Circuits, Devices Sys., 1997, 144, (6), pp. 313-317.
16. Basterretxea, K., Tarela, J.M. "Approximation of sigmoid function and the derivative for artificial neurons", in Mastorakis, N. (Ed.): 'Advances in neural networks and applications' (WSES Press, Athens, 2001), pp. 397-401.
17. Skrbek M., "Fast Neural Network Implementation", Neural Network World 5/99, pp. 375-391, 1999.
18. Druzbik, T., Havel, V., Martinovic, J., Snasel, V., Vlcek, K. "Digital neural network for concept lattices generation", The 6th Conference on Scientific Computing in Electrical Engineering, SCEE 2006, Sinaia, Romania, pp. 158-159.
19. Havel, V., Vlcek, K., "Feasibility of Image Compression in FPGA based Neural Networks", In IEEE DDECS 07, Cracow, Poland, ISBN 1-4244-1161-0,pp.329-331, April 11-13,2007.
20. Havel, V. "An Implementation of a Perceptron with an Arbitrary Activation Function", International Workshop - Control and Information Technology, IWCIT, Ostrava, 2007.
21. Reynolds, P.D.: Algorithm Implementation in FPGAs Demonstrated Through Neural Network Inversion on the SRC-6e, Thesis, Baylor University. Waco, Texas, 2005.
22. Havel V., Vlcek K., Mitrych J. "Neural Network Architectures for Image Compression", In IFAC PDS 2004, Nov. 18-19, 2004, Cracow, Poland, Gliwice, Poland: Silesian University of Technology, , 2004, 389-394, 83-908409-8-7.