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Volumn , Issue , 1998, Pages 112-117

Handling cross interferences by cyclic cache line coloring

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY;

EID: 77951543790     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.1998.727180     Document Type: Conference Paper
Times cited : (4)

References (18)
  • 1
    • 84976815037 scopus 로고
    • Register allocation and spilling via graph coloring
    • ACM, ACM, 1982. SIGPLAN Notices June
    • G. J. Chaitin. Register allocation and spilling via graph coloring. In Proceedings of the SIGPLAN '82 Symposium on Compiler Construction, pages 98-105. ACM, ACM, 1982. Available as SIGPLAN Notices 17(6) June 1982.
    • (1982) Proceedings of the SIGPLAN '82 Symposium on Compiler Construction , vol.17 , Issue.6 , pp. 98-105
    • Chaitin, G.J.1
  • 2
    • 84976859799 scopus 로고
    • Unifying data and control transformations for distributed shared-memory machines
    • June
    • M. Cierniak and W. Li. Unifying data and control transformations for distributed shared-memory machines. SIGPLAN Notices., 30(6):205-217, June 1995.
    • (1995) SIGPLAN Notices. , vol.30 , Issue.6 , pp. 205-217
    • Cierniak, M.1    Li, W.2
  • 3
    • 84976745804 scopus 로고    scopus 로고
    • Tile size selection using cache organization and data layout
    • D. W. Wall, editor of ACM SIGPLAN Notices, New York, NY, USA, June 1995. ACM Press
    • S. Coleman and K. S. McKinley. Tile size selection using cache organization and data layout. In D. W. Wall, editor, ACM SIGPLAN '95 Conference on Programming Language Design and Implementation (PLDI), volume 30(6) of ACM SIGPLAN Notices, pages 279290, New York, NY, USA, June 1995. ACM Press.
    • ACM SIGPLAN '95 Conference on Programming Language Design and Implementation (PLDI) , vol.30 , Issue.6 , pp. 279-290
    • Coleman, S.1    McKinley, K.S.2
  • 4
    • 0029195621 scopus 로고
    • The meeting graph: A new model for loop cyclic register allocation
    • L. Bic, W. Bohm, P. Evripidou, and J.-L. Gaudiot, editors, Limas-sol, Cyprus, June 27-29. ACM Press
    • C. Eisenbeis, S. Lelait, and B. Marmol. The meeting graph: A new model for loop cyclic register allocation. In L. Bic, W. Bohm, P. Evripidou, and J.-L. Gaudiot, editors, Proceedings PACT'95, pages 264-267, Limas-sol, Cyprus, June 27-29, 1995. ACM Press.
    • (1995) Proceedings PACT'95 , pp. 264-267
    • Eisenbeis, C.1    Lelait, S.2    Marmol, B.3
  • 7
    • 84976845365 scopus 로고
    • A register allocation framework based on hierarchical cyclic interval graphs
    • of LNCS Springer-Verlag
    • L. Hendren, G. Gao, E. Altman, and C. Mukerji. A register allocation framework based on hierarchical cyclic interval graphs. In Proc. 4th Int. Conf. Compiler Construction, volume 641 of LNCS, pages 176191. Springer-Verlag, 1992.
    • (1992) Proc 4th Int. Conf. Compiler Construction , vol.641 , pp. 176191
    • Hendren, L.1    Gao, G.2    Altman, E.3    Mukerji, C.4
  • 13
    • 25544469671 scopus 로고    scopus 로고
    • Improving cache performance through tiling and data alignment
    • Springer LNCS 1253
    • P. R. Panda, H. Nakamura, N. D. Dutt, and A. Nico-lau. Improving cache performance through tiling and data alignment. In IRREGULAR 1997, pages 167185. Springer LNCS 1253, 1997.
    • (1997) IRREGULAR 1997 , pp. 167185
    • Panda, P.R.1    Nakamura, H.2    Dutt, N.D.3    Nico-Lau, A.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.