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Volumn , Issue , 2004, Pages

Chip multithreading systems need a new operating system scheduler

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION PERFORMANCE; CHIP MULTIPROCESSING; CHIP MULTITHREADING; HARDWARE MULTITHREADING; OPERATING SYSTEMS; PROCESSOR ARCHITECTURES; PROCESSOR PIPELINES; SIMULATION EXPERIMENTS;

EID: 77951460421     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1133572.1133597     Document Type: Conference Paper
Times cited : (13)

References (19)
  • 2
    • 0031594020 scopus 로고    scopus 로고
    • An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors
    • June
    • Jack Lo et al., "An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors", ISCA, June 1998.
    • (1998) ISCA
    • Lo, J.1
  • 3
    • 0001087280 scopus 로고    scopus 로고
    • Hyper-Threading Technology Architecture and Microarchitecture
    • Deborah T. Marr et al., "Hyper-Threading Technology Architecture and Microarchitecture", Intel Technology Journal Q1, 2002.
    • (2002) Intel Technology Journal Q1
    • Marr, D.T.1
  • 5
    • 0025431380 scopus 로고
    • APRIL: A Processor Architecture for Multiprocessing
    • June
    • Anant Agrawal, Beng-Hong Lim, David Kranz and John Kubiatowicz, "APRIL: A Processor Architecture for Multiprocessing", ISCA, June 1990.
    • (1990) ISCA
    • Agrawal, A.1    Lim, B.-H.2    Kranz, D.3    Kubiatowicz, J.4
  • 6
    • 77951427473 scopus 로고
    • Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations
    • October
    • James Laudon, Anoop Gupta, and Mark Horowitz, "Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations", ASPLOS VI, October 1994.
    • (1994) ASPLOS VI
    • Laudon, J.1    Gupta, A.2    Horowitz, M.3
  • 7
    • 77951445328 scopus 로고    scopus 로고
    • Converting thread-level parallelism into instruction-level parallelism via simultaneous multithreading
    • August
    • Jack Lo, Susan Eggers, Joel Emer, Henry Levy, Rebecca Stamm, and Dean Tullsen, "Converting thread-level parallelism into instruction-level parallelism via simultaneous multithreading", ACM TOCS 15, 2, August 1997.
    • (1997) ACM TOCS 15 , vol.2
    • Lo, J.1    Eggers, S.2    Emer, J.3    Levy, H.4    Stamm, R.5    Tullsen, D.6
  • 8
    • 77951494384 scopus 로고    scopus 로고
    • Sun Microsystems web site, http://www.sun.com/processors/throughput/ datasheet.html
  • 9
    • 77951474008 scopus 로고    scopus 로고
    • Intel web site, http://www.intel.com/pressroom/archive/speeches/ otellini20030916.htm
  • 10
    • 0042455211 scopus 로고    scopus 로고
    • Symbiotic Jobscheduling for a Simultaneous Multithreading Machine
    • November
    • Allan Snavely and Dean Tullsen, "Symbiotic Jobscheduling for a Simultaneous Multithreading Machine", In ASPLOS IX, November 2000.
    • (2000) ASPLOS IX
    • Snavely, A.1    Tullsen, D.2
  • 11
    • 0042455211 scopus 로고    scopus 로고
    • Symbiotic Jobscheduling with Priorities for a Simultaneous Multithreading Processor
    • Allan Snavely, Dean Tullsen, and Geoff Voelker, "Symbiotic Jobscheduling with Priorities for a Simultaneous Multithreading Processor", SIGMETRICS, 2002.
    • (2002) SIGMETRICS
    • Snavely, A.1    Tullsen, D.2    Voelker, G.3
  • 13
    • 34547715870 scopus 로고    scopus 로고
    • Initial Observations of the Simultaneous Multithreading Pentium 4 Processor
    • September
    • Nathan Tuck and Dean M. Tullsen, "Initial Observations of the Simultaneous Multithreading Pentium 4 Processor", PACT, September 2003.
    • (2003) PACT
    • Tuck, N.1    Tullsen, D.M.2
  • 14
    • 0029200683 scopus 로고
    • Simultaneous Multithreading: Maximizing On-Chip Parallelism
    • June
    • Dean M. Tullsen, Susan J. Eggers, and Henry M. Levy, "Simultaneous Multithreading: Maximizing On-Chip Parallelism", ISCA, June 1995.
    • (1995) ISCA
    • Tullsen, D.M.1    Eggers, S.J.2    Levy, H.M.3
  • 19
    • 0033722744 scopus 로고    scopus 로고
    • Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing
    • L. Barroso et al., "Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing", ISCA'00.
    • ISCA'00
    • Barroso, L.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.