Mapping the FDTD application to many-core chip architectures

Proceedings of the International Conference on Parallel Processing

Volumn , Issue , 2009, Pages 309-316

  Orozco, Daniel ^a   Gao, Guang ^a  

^a UNIVERSITY OF DELAWARE   (United States)

Author keywords

Bandwidth Reduction; Code Optimization; Parallel Tiling; Stencil Computations

Indexed keywords

BANDWIDTH REDUCTIONS; CHIP ARCHITECTURE; CODE OPTIMIZATION; CODE OPTIMIZATION TECHNIQUE; COMPILER OPTIMIZATIONS; CURRENT TRENDS; DATA CACHES; FINE GRAINS; FINITE DIFFERENCE TIME DOMAINS; MANY-CORE; MANY-CORE ARCHITECTURE; MULTI-THREADING; ON CHIP MEMORY; ON CHIPS; ON-CHIP PARALLELISM; PERFORMANCE IMPROVEMENTS; STENCIL COMPUTATIONS; TIME SKEWING;

BANDWIDTH; FINITE DIFFERENCE TIME DOMAIN METHOD; MAPPING; MULTITASKING; OPTIMIZATION; PROGRAM COMPILERS;

COMPUTER ARCHITECTURE;

EID: 77951447129     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2009.44     Document Type: Conference Paper

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