Statistical approach to low power and high volume pineview atom-based SoC design

2009 International SoC Design Conference, ISOCC 2009

Volumn , Issue , 2009, Pages 228-231

  Sutanthavibul, Suphachai ^a   Hamid, Azydee ^b  

^a INTEL CORPORATION   (United States)

^b Intel Technology Malaysia Sdn Bhd   (Malaysia)

Author keywords

Component; Low power; SoC; Statistical; Yields

Indexed keywords

DESIGN TEAM; FABRICATION PROCESS; HIGH YIELD; IP BLOCK; LOW POWER; POST-SILICON; POWER MODEL; PROCESS VARIATION; SOC DESIGNS; STATISTICAL APPROACH; STATISTICAL DESIGN; SUBMICRON;

PROGRAMMABLE LOGIC CONTROLLERS; STATISTICS;

DESIGN;

EID: 77951437821     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCDC.2009.5423804     Document Type: Conference Paper

References (3)

1. Kelin Kuhn, et al., "Managing Process Variation in Intel's 45nm CMOS Process", Intel Technology Journal (ITJ), Volumn 12, Issue 2, 2008, p93-109
2. Rajiv Joshi, Rouwaida Kanj, "Statistical-aware Designs for the nm Era", IC Design and Technology, 2009
3. Gao Yu, Wei Dong, Zhou Feng, Peng Li, "Statistical Static Timing Analysis Considering Process Variation Model Uncertainty", IEEE Transcation on Computer-Aided Design of Integrated Circutis and Systems, 2008