Wafer dicing process optimization and characterization for C90 low-k wafer technology

Proceedings of the Electronic Packaging Technology Conference, EPTC

Volumn , Issue , 2009, Pages 889-892

  Shi, Koh Wen ^a   Yow, K Y ^a   Rachel, Khoo ^a   Calvin, Lo ^a  

^a FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTINUOUS IMPROVEMENTS; CRITICAL PROCESS PARAMETERS; CUT DEPTH; CUT QUALITY; DEVICE RELIABILITY; ELECTRICAL TESTS; EXPERIMENTAL STUDIES; MACHINING PARAMETERS; MECHANICAL DICING; METAL DENSITY; ON CURRENTS; OPTICAL MICROSCOPES; PRODUCTION ENVIRONMENTS; SEM; SPINDLE ROTATION; TEST WAFERS; VISUAL INSPECTION; WAFER DICING; WAFER TECHNOLOGY; WORST CASE; YIELD LOSS;

CHARACTERIZATION; DESIGN OF EXPERIMENTS; ELECTRONICS PACKAGING; FOCUSED ION BEAMS; MACHINING; MACHINING CENTERS; OPTIMIZATION; REGRESSION ANALYSIS; RELIABILITY ANALYSIS; SCANNING ELECTRON MICROSCOPY; VISUAL COMMUNICATION;

ANALYSIS OF VARIANCE (ANOVA);

EID: 77950927104     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2009.5416419     Document Type: Conference Paper

References (1)

1. Wang ZhiJie, Wang, S., Wang, J.H., Lee, S., Yao Su Ying, Han, R., Su, Y.Q., "300mm Low-k Wafer Dicing Saw Study", Electronic Packaging Technology, Sept. 2005, pp. 262-268.