300mm low K wafer dicing saw study

2005 6th International Conference on Electronics Packaging Technology

Volumn 2005, Issue , 2005, Pages 262-268

  Wang, ZhiJie ^a   Wang, Sonder ^b   Wang, J H ^b   Lee, Stephen ^b   SuYing, Yao ^a   Han, Richard ^b   Su, Y Q ^b  

^a TIANJIN UNIVERSITY   (China)

^b Freescale Inc   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; INTERCONNECTION NETWORKS; OPTIMIZATION; RELIABILITY; SEMICONDUCTING SILICON; SILICA;

DICING BLADES; INTERCONNECT DELAY; SPINDLE SPEED; WAFER DICING;

WSI CIRCUITS;

EID: 33846279746     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICEPT.2005.1564687     Document Type: Conference Paper

References (3)

1. T. Scherban, B.Sun, J.Blaine, C.Block, B.Jin, E.Andideh., "interfacial adhesion of copper-low k interconnects", in 2001 IEEE International Interconnect Technology Conference Proceeedings, pp257-259.
2. P.Nunam, "The challenge of Low k, Issues and Considerations for Accelerated Performance", Yield Management Solutions, Spring 2000, P17.
3. International Technology Roadmaps for Semiconductors 2004