Gadara nets: Modeling and analyzing lock allocation for deadlock avoidance in multithreaded software

Proceedings of the IEEE Conference on Decision and Control

Volumn , Issue , 2009, Pages 4971-4976

  Wang, Yin ^c   Liao, Hongwei ^a   Reveliotis, Spyros ^b   Kelly, Terence ^c   Mahlke, Scott ^a   Lafortune, Stéphane ^a  

^a The Department of Civil and Environmental Engineering   (United States)

^b Georgia Institute of Technology   (United States)

^c HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOCKS (FASTENERS); MANUFACTURE; MEMORY ARCHITECTURE; PARALLEL PROGRAMMING; PETRI NETS; SOFTWARE ARCHITECTURE;

BEHAVIORAL ANALYSIS; DEADLOCK ANALYSIS; DEADLOCK AVOIDANCE; DISCRETE EVENT CONTROL; FORMAL DEFINITION; MULTI-THREADED PROGRAMS; MULTICORE ARCHITECTURES; MULTITHREADED SOFTWARES;

MULTICORE PROGRAMMING;

EID: 77950810847     PISSN: 07431546     EISSN: 25762370     Source Type: Conference Proceeding    
DOI: 10.1109/CDC.2009.5399950     Document Type: Conference Paper

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