FPGA based selective harmonic elimination pulse width modulation technique

2009 4th International Design and Test Workshop, IDT 2009

Volumn , Issue , 2009, Pages

  Saied, Basil M ^a   Dawwd, Shefa A ^a   Al Soufi, Ahmad S ^a  

^a UNIVERSITY OF MOSUL   (Iraq)

Author keywords

FPGA; SHEPWM; VHDL; VSI

Indexed keywords

ARTIFICIAL NEURAL NETWORK; DRIVE VOLTAGE; HARDWARE DESIGN; LOW COSTS; MODULATION INDEXES; REAL TIME; SELECTED HARMONIC ELIMINATION; SELECTIVE HARMONIC ELIMINATION;

COUNTING CIRCUITS; DESIGN; ELECTRIC INVERTERS; NEURAL NETWORKS; NONLINEAR EQUATIONS; PULSE MODULATION; PULSE WIDTH MODULATION; TECHNICAL PRESENTATIONS; ULTRASONIC TRANSDUCERS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 77950430540     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IDT.2009.5404137     Document Type: Conference Paper

References (6)

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3. Basil M. Saied, Ahmad S. Al-Soufi,"Intelligent Systems Based Selective Harmonic Elimination For Single Phase Voltage Source Inverter, Al-Raffidain Eng. Proc., Vol. 16, No. 3, 2008.
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6. Zhu, Jihan; Sutton, Peter, "FPGA Implementations of Neural Networks - a Survey of a Decade of Progress", International Conference on Field Programmable Logic and Applications (FPL'03), pp. 1062-1066, LNCS 2778, Springer Verlag, Berlin, Heidelberg, 2003.