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Volumn 57, Issue 4, 2010, Pages 919-927

Short-circuit capability of SiC buried-gate static induction transistors: Basic mechanism and impacts of channel width on short-circuit performance

Author keywords

Device simulation; Power devices; Short circuit operation; Static induction transistors (SITs); Unipolar devices

Indexed keywords

CIRCUIT OPERATION; DEVICE SIMULATIONS; POWER DEVICES; STATIC INDUCTION TRANSISTORS; UNIPOLAR DEVICES;

EID: 77950300737     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2040665     Document Type: Article
Times cited : (9)

References (12)
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    • An experimental and numerical study on the forward biased SOA of IGBTs
    • Mar.
    • H. Hagino, J. Yamashita, A. Uenishi, and H. Haruguchi, "An experimental and numerical study on the forward biased SOA of IGBTs," IEEE Trans. Electron Devices, vol.43, no.3, pp. 490-500, Mar. 1996.
    • (1996) IEEE Trans. Electron Devices , vol.43 , Issue.3 , pp. 490-500
    • Hagino, H.1    Yamashita, J.2    Uenishi, A.3    Haruguchi, H.4
  • 5
    • 0016497460 scopus 로고
    • Field-effect transistors versus analog transistors (static induction transistors)
    • Apr.
    • J. Nishizawa, T. Terasaki, and J. Shibata, "Field-effect transistors versus analog transistors (static induction transistors)," IEEE Trans. Electron Devices, vol.ED-22, no.4, pp. 185-197, Apr. 1975.
    • (1975) IEEE Trans. Electron Devices , vol.ED-22 , Issue.4 , pp. 185-197
    • Nishizawa, J.1    Terasaki, T.2    Shibata, J.3
  • 7
    • 39749191885 scopus 로고    scopus 로고
    • Buried gate static induction transistor in 4H-SiC (SiC-BGSITs) with ultra low ON-resistance
    • Y. Tanaka, K. Yano, M. Okamoto, A. Takatsuka, K. Arai, and T. Yatsuo, "Buried gate static induction transistor in 4H-SiC (SiC-BGSITs) with ultra low ON-resistance," in Proc. 19th ISPSD, 2007, pp. 93-96.
    • (2007) Proc. 19th ISPSD , pp. 93-96
    • Tanaka, Y.1    Yano, K.2    Okamoto, M.3    Takatsuka, A.4    Arai, K.5    Yatsuo, T.6
  • 12
    • 0023295763 scopus 로고
    • Safe operating area for 1200-V nonlatchup bipolar-mode MOSFETs
    • Feb.
    • A. Nakagawa, Y. Yamaguchi, K. Watanabe, and H. Ohashi, "Safe operating area for 1200-V nonlatchup bipolar-mode MOSFETs," IEEE Trans. Electron Devices, vol.ED-34, no.2, pp. 351-355, Feb. 1987.
    • (1987) IEEE Trans. Electron Devices , vol.ED-34 , Issue.2 , pp. 351-355
    • Nakagawa, A.1    Yamaguchi, Y.2    Watanabe, K.3    Ohashi, H.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.