Dual-source-line-bias scheme to improve the read margin and sensing accuracy of STTRAM in sub-90-nm nodes

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 57, Issue 3, 2010, Pages 208-212

  Chatterjee, Subho ^a   Salahuddin, Sayeef ^b   Mukhopadhyay, Saibal ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Dual source line bias (DSLB); Leakage current; Magnetic tunneling junction (MTJ); Read margin; Spin torque transfer random access memory (STTRAM)

Indexed keywords

LEAKAGE CURRENTS; MAGNETIC DEVICES; MAGNETIC LEAKAGE; NANOTECHNOLOGY;

BIASING TECHNIQUES; DUAL SOURCE; MAGNETIC TUNNELING JUNCTIONS; RANDOM ACCESS MEMORY; READ MARGIN; SENSING ACCURACY; SPIN TORQUE TRANSFER; TRANSISTOR LEAKAGE;

RANDOM ACCESS STORAGE;

EID: 77950300351     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2010.2040308     Document Type: Article

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