A 90mW/GFlop 3.4GHz reconfigurable fused/continuous multiply-accumulator for floating-point and integer operands in 65nm

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2010, Pages 252-257

  Jain, Shailendra ^a   Erraguntla, Vasantha ^a   Vangal, Sriram R ^a   Hoskote, Yatin ^a   Borkar, Nitin ^a   Mandepudi, Tulasi ^a   Karthik, V P ^b  

^a INTEL CORPORATION   (United States)

^b Analog Devices India Pvt Ltd   (India)

Author keywords

[No Author keywords available]

Indexed keywords

65NM CMOS TECHNOLOGY; BIT LEVEL; COMPACT DESIGNS; ENERGY CONTROL; ENERGY EFFICIENT; FINE-GRAINED POWER; IDLE MODE; LEAKAGE POWER; PIPELINED MULTIPLIERS; POWER GATINGS; RE-CONFIGURABLE; SINGLE CYCLE; TOTAL ENERGY;

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DESIGN; DIGITAL ARITHMETIC; ENERGY EFFICIENCY; FREQUENCY MULTIPLYING CIRCUITS;

EMBEDDED SYSTEMS;

EID: 77949949584     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.Design.2010.59     Document Type: Conference Paper

References (3)

1. Sriram Vangal et al., "A 5 GHz Floating-point Multiply Accumulator in 90nm Dual VT CMOS", ISSCC 2003, Session 19, Processor Building blocks, Paper 19.1.
2. J.W. Tschanz et al, "Dynamic sleep transistor and body bias for active leakage power control of microprocessors", IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1838-1845, Nov. 2003.
3. Sriram Vangal et al., "A 6.2-GFlops Floating-point Multiply Accumulator with Conditional Normalization", IEEE Journal of Solid State Circuits, Vol. 41, No. 10, Oct. 2006, pp.2314-2322