Lot-sizing and scheduling problem with earliness tardiness and setup penalties

Computers and Industrial Engineering

Volumn 58, Issue 3, 2010, Pages 363-372

  Supithak, Wisut ^a   Liman, Surya D ^b   Montes, Elliot J ^b  

^a KASETSART UNIVERSITY   (Thailand)

^b Department of Electrical and Computer Engineering   (United States)

Author keywords

Earliness; Earliness tardiness; Lot sizing; Lot sizing and scheduling; Scheduling; Tardiness

Indexed keywords

ASSIGNMENT PROBLEMS; DUE DATES; EARLINESS-TARDINESS; HOLDING COSTS; LARGE SIZES; LOT SIZING; LOT-SIZING AND SCHEDULING; OPTIMAL TIMING; PRODUCTION LOT SIZE; SCHEDULING PROBLEM; SEARCH ALGORITHMS; SETUP COSTS; SMALL SIZE; TARDINESS PENALTIES;

COSTS; LEARNING ALGORITHMS;

PROBLEM SOLVING;

EID: 77949653622     PISSN: 03608352     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.cie.2008.10.005     Document Type: Article

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