Challenges in using optical lithography for the building of a 22 nm node 6T-SRAM cell

Microelectronic Engineering

Volumn 87, Issue 5-8, 2010, Pages 993-996

  Ercken, M ^a   Altamirano Sanchez, E ^a   Baerts, C ^a   Brus, S ^a   De Backer, J ^a   Delvaux, C ^a   Demand, M ^a   Horiguchi, N ^a   Locorotondo, S ^a   Vandeweyer, T ^a   Veloso, A ^a   Verhaegen, S ^a  

^a IMEC   (Belgium)

Author keywords

22 nm node; Immersion lithography; Litho friendly circuit layout; Patterning; SRAM scaling

Indexed keywords

32 NM TECHNOLOGY; 6T-SRAM; CIRCUIT LAYOUTS; FINFET DEVICES; GATE LEVELS; IMMERSION LITHOGRAPHY; METAL LEVELS; OPTICAL LITHOGRAPHY; PATTERNING PROCESS; SRAM CELL;

GATES (TRANSISTOR); PHOTOLITHOGRAPHY; STATIC RANDOM ACCESS STORAGE;

NANOTECHNOLOGY;

EID: 76949104698     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2009.11.119     Document Type: Article

References (6)

1. Veloso A., et al. IEEE IEDM Technol. Dig. (2008) 861-863
2. Kawasaki H., et al. IEEE IEDM Technnol. Dig. (2008) 237-240
3. Verhaegen S., et al. Proc. SPIE 5756 (2005) 120-130
4. M. Ercken et al., Proc. Interf., CD published by Fujifilm Electronic Materials, 2004.
5. Altamirano-Sanchez E., et al. Proc. Dry Process Symposium (2009) 239-240
6. Veloso A., et al. IEEE IEDM Technol. Dig. (2009) 301-304