The potential for economic application of maskless lithography in semiconductor manufacturing

IEEE Transactions on Semiconductor Manufacturing

Volumn 23, Issue 1, 2010, Pages 39-52

  Berglund, C Neil ^a   Leachman, Robert C ^b  

^a Northwest Technology Group   (United States)

^b DEPARTMENT OF INDUSTRIAL ENGINEERING AND OPERATIONS RESEARCH   (United States)

Author keywords

Economic analysis; Electron beam lithography; Maskless lithography; Semiconductor manufacturing; Silicon processes

Indexed keywords

BUSINESS CASE; FABRICATION OPERATIONS; HARD LAYERS; MASK LESS; MASK-LESS LITHOGRAPHY; PRODUCT LIFETIME; SEMICONDUCTOR MANUFACTURING; SILICON PROCESS; SILICON PROCESSES; TECHNOLOGY NODES; THROUGHPUT CAPABILITY;

ECONOMIC ANALYSIS; ELECTRON BEAM LITHOGRAPHY; ELECTRON BEAMS; MANUFACTURE; SEMICONDUCTING SILICON; SILICON WAFERS; THROUGHPUT;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 76849111506     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2009.2039247     Document Type: Article

References (6)

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4. S. Hector, "Maskless lithography (ML2) background," presented at the SEMATECH Maskless Lithography Workshop Meeting, Jan. 2005.
5. SEMATECH, Cost/resource model version 4.4.1 SEMATECH Technology Transfer Doc. 96113202A-TR, 1996.
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