Path-based, randomized, oblivious, minimal routing

2nd International Workshop on Network on Chip Architectures, NoCArc 2009, In conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO42

Volumn , Issue , 2009, Pages 23-28

  Cho, Myong Hyon ^a   Lis, Mieszko ^a   Shim, Keun Sup ^a   Kinsy, Michel ^a   Devadas, Srinivas ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

C.2.1 network architecture and design : network communications

Indexed keywords

C.2.1 [NETWORK ARCHITECTURE AND DESIGN]: NETWORK COMMUNICATIONS; DIMENSION-ORDERED ROUTING; DIVERSE ROUTING; FORWARD PACKETS; HARDWARE COST; MESH GEOMETRY; NETWORK COMMUNICATIONS; NETWORK ON CHIP; OBLIVIOUS ROUTING; PATH-BASED; RANDOMIZED DECISIONS; SOURCE NODES; VIRTUAL CHANNELS;

DISTRIBUTED COMPUTER SYSTEMS; PROM; ROUTERS; ROUTING ALGORITHMS; VLSI CIRCUITS;

NETWORK ARCHITECTURE;

EID: 76749118545     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1645213.1645220     Document Type: Conference Paper

References (17)

1. G.-M. Chiu. The Odd-Even Turn Model for Adaptive Routing. IEEE Trans. Parallel Distrib. Syst., 11(7):729-738, 2000.
2. W. J. Dally and H. Aoki. Deadlock-free adaptive routing in multicomputer networks using virtual channels. IEEE Transactions on Parallel and Distributed Systems, 04(4):466-475, 1993.
3. W. J. Dally and C. L. Seitz. Deadlock-Free Message Routing in Multiprocessor Interconnection Networks. IEEE Trans. Computers, 36(5):547-553, 1987.
4. W. J. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2003.
5. C. J. Glass and L. M. Ni. The turn model for adaptive routing. J. ACM, 41(5):874-902, 1994.
6. P. Gratz, B. Grot, and S. W. Keckler. Regional Congestion Awareness for Load Balance in Networks-on-Chip. In In Proc. of the 14th Int. Symp. on High-Performance Computer Architecture (HPCA), pages 203-214, Feb. 2008.
7. H. J. Kim, D. Park, T. Theocharides, C. Das, and V. Narayanan. A Low Latency Router Supporting Adaptivity for On-Chip Interconnects. In Proceedings of Design Automation Conference, pages 559-564, June 2005.
8. M. Lis, K. S. Shim, M. H. Cho, and S. Devadas. Guaranteed in-order packet delivery using Exclusive Dynamic Virtual Channel Allocation. Technical Report CSAIL-TR-2009-036 (http://hdl.handle.net/1721.1/46353), Massachusetts Institute of Technology, Aug. 2009.
9. T. Nesson and S. L. Johnsson. ROMM Routing: A Class of Efficient Minimal Routing Algorithms. In in Proc. Parallel Computer Routing and Communication Workshop, pages 185-199, 1994.
10. T. Nesson and S. L. Johnsson. ROMM routing on mesh and torus networks. In Proc. 7th Annual ACM Symposium on Parallel Algorithms and Architectures SPAA'95, pages
11. D. Seo, A. Ali, W.-T. Lim, N. Rafique, and M. Thottethodi. Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks. In Proceedings of the 32nd Annual International Symposium on Computer Architecture (ISCA 2005), pages 432-443, 2005.
12. rd ACM/IEEE International Symposium on Networks-on-Chip, May 2009.
13. A. Singh, W. J. Dally, A. K. Gupta, and B. Towles. GOAL: a load-balanced adaptive routing algorithm for torus networks. SIGARCH Comput. Archit. News, 31(2):194-205, 2003.
14. A. Singh, W. J. Dally, B. Towles, and A. K. Gupta. Globally Adaptive Load-Balanced Routing on Tori. IEEE Comput. Archit. Lett., 3(1), 2004.
15. B. Towles and W. J. Dally. Worst-case traf.c for oblivious routing functions. In SPAA '02: Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures, pages 1-8, 2002.
16. B. Towles, W. J. Dally, and S. Boyd. Throughput-centric routing algorithm design. In SPAA '03: Proceedings of the fifteenth annual ACM symposium on Parallel algorithms and architectures, pages 200-209, 2003.
17. L. G. Valiant and G. J. Brebner. Universal schemes for parallel communication. In STOC '81: Proceedings of the thirteenth annual ACM symposium on Theory of computing, pages 263-277, 1981.