Architectures and arithmetic for low static power consumption in nanoscale CMOS

VLSI Design

Volumn 2009, Issue , 2009, Pages

  Nilsson, Peter ^a  

^a LUND UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

BIT-PARALLEL; BIT-SERIAL; CMOS TECHNOLOGY; DIGIT-SERIAL; FILTER ARCHITECTURE; LEAKAGE REDUCTION; LOW STATIC POWER; LOWER-POWER CONSUMPTION; NANOSCALE CMOS; POWER RATIO; POWER REDUCTIONS; SIMULATION RESULT; STATIC POWER; STATIC POWER CONSUMPTION; WORD LENGTH;

CMOS INTEGRATED CIRCUITS; FIR FILTERS;

IIR FILTERS;

EID: 76649094950     PISSN: 1065514X     EISSN: None     Source Type: Journal    
DOI: 10.1155/2009/749272     Document Type: Article

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