An integrated linear regulator with fast output voltage transition for SRAM yield improvement

Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Volumn , Issue , 2009, Pages 329-332

  Tseng, Chun Yen ^a,b   Huang, Po Chiun ^a,b   Wang, Li Wen ^a,b  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT EFFICIENCY; CURRENT LOADINGS; FEED-BACK LOOP; FULLY INTEGRATED; LINEAR REGULATORS; LOAD REGULATIONS; MODE SWITCHES; OUTPUT VOLTAGES; REFERENCE-TRACKING; SRAM CELL; TRANSITION SPEED; YIELD IMPROVEMENT;

STATIC RANDOM ACCESS STORAGE;

LAWS AND LEGISLATION;

EID: 76249125934     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2009.5357161     Document Type: Conference Paper

References (4)

1. F.-S. Lai, et. al, On-chip voltage down, converter to improve SRAM read/write margin, and static power for sub-nano CMOS technology, IEEE J. Solid-State Circuits, vol.42, pp. 2061-2070, Sep. 2007.
2. P. Hazucha, et. al, Area-efficient linear regulator with ultra-fast load regulation, IEEE J. Solid-State Circuits, vol.40, pp. 933-940, Apr. 2005.
3. S. Lau, et. al, A. Low-Dropout Regulator for SoC with Q-Reduction, IEEE J. Solid-State Circuits, vol.42, pp. 658-664, May 2007.
4. R. Milliken, et. al, Full On-Chip CMOS Low-Dropout Voltage Regulator, IEEE Trans. Circuits Syst I, vol.54, pp. 1879-1890, Dec. 2007.