Power integrity optimization of 3D chips stacked through TSVs

2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09

Volumn , Issue , 2009, Pages 105-108

  Ahmad, Waqar ^a   Zheng, Li Rong ^a   Weerasekera, Roshan ^a   Chen, Qiang ^a   Weldezion, Awet Yemane ^a   Tenhunen, Hannu ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

Peripheral TSVs; Power distribution network; Power integrity

Indexed keywords

3-D ICS; DECOUPLING CAPACITOR; DESIGN TRADEOFF; ON-CHIP POWER DISTRIBUTION; POWER DISTRIBUTION NETWORK; POWER INTEGRITY;

ABERRATIONS; DISTRIBUTED PARAMETER NETWORKS; ELECTRIC NETWORK ANALYSIS; QUALITY ASSURANCE; THREE DIMENSIONAL;

CHIP SCALE PACKAGES;

EID: 74549182688     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEPS.2009.5338467     Document Type: Conference Paper

References (8)

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