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Volumn , Issue , 2009, Pages 5-8

A low-power 1.92MHz CT ΔΣ modulator with 5-bit successive approximation quantizer

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK-JITTER; CMOS TECHNOLOGY; DELAY COMPENSATION; DELTA SIGMA MODULATOR; DELTA-SIGMA; DYNAMIC RANGE; EXPONENTIAL GROWTH; LIMITING FACTORS; LOW POWER; MEASUREMENT RESULTS; MULTI-BITS; POWER CONSUMPTION; QUANTIZERS; SUCCESSIVE APPROXIMATIONS; SUCCESSIVE-APPROXIMATION ADC; WIDE-BAND;

EID: 74049139558     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2009.5280910     Document Type: Conference Paper
Times cited : (9)

References (6)
  • 2
    • 33845630644 scopus 로고    scopus 로고
    • A 20-mW 640-MHz CMOS Continuous-Time ΣΔ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB
    • December
    • J. Mittereger, C. Ebner, et al, "A 20-mW 640-MHz CMOS Continuous-Time ΣΔ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB" IEEE J. Solid-State Circuits, Vol. 41, No. 12, pp. 2641-2649, December 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.12 , pp. 2641-2649
    • Mittereger, J.1    Ebner, C.2
  • 3
    • 3042737899 scopus 로고    scopus 로고
    • A70-mW 300-MHz CMOS continuous-time sigma-delta ADC with 15-MHz bandwidth and 11-bits of resolution
    • Jul
    • S. Paton, A. Di Giandomenico, L. Hernández, A. Wiesbauer, P. Potscher, and M. Clara, "A70-mW 300-MHz CMOS continuous-time sigma-delta ADC with 15-MHz bandwidth and 11-bits of resolution," IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1056-1062, Jul. 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , Issue.7 , pp. 1056-1062
    • Paton, S.1    Di Giandomenico, A.2    Hernández, L.3    Wiesbauer, A.4    Potscher, P.5    Clara, M.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.