A low-complexity synchronization based cache coherence solution for many cores

Proceedings - IEEE 9th International Conference on Computer and Information Technology, CIT 2009

Volumn 1, Issue , 2009, Pages 69-75

  Lin, Wei ^a,b   Fan, DongRui ^a   Huang, He ^a,b   Yuan, Nan ^a,b   Ye, Xiaochun ^a,b  

^a INSTITUTE OF COMPUTING TECHNOLOGY   (China)

^b UNIVERSITY OF CHINESE ACADEMY OF SCIENCES   (China)

Author keywords

Cache coherence; Multiple writer; Scope consistency; Word dirty bits; Write validate

Indexed keywords

CACHE COHERENCE; CHIP AREAS; COHERENCE PROTOCOL; GODSON-T; LOW-COMPLEXITY; MANY CORE; MULTIPLE WRITER; ONE CHIP; PARALLEL PERFORMANCE; PROCESSOR PERFORMANCE; SCOPE CONSISTENCY; SPECIAL HARDWARE;

BIOINFORMATICS; INFORMATION TECHNOLOGY; SYNCHRONIZATION;

COMPUTER ARCHITECTURE;

EID: 73449135134     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CIT.2009.100     Document Type: Conference Paper

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