Numerical analysis of destruction modes in IGBT chips

2009 13th European Conference on Power Electronics and Applications, EPE '09

Volumn , Issue , 2009, Pages

  Knipper, U ^a   Pfirsch, F ^b   Raker, T ^b   Niedermeyr, J ^b   Wachutka, G ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

Bipolar device; Discrete power device; IGBT; Reliability; Robustness

Indexed keywords

ACTIVE PARTS; AVALANCHE BREAKDOWN; BIPOLAR DEVICE; DESIGN OPTIMIZATION; DISCRETE POWER DEVICES; EDGE TERMINATION; ELECTRICAL CROSSTALKS; IGBT-CHIP; OPERATING AREA; RELIABILITY ROBUSTNESS;

ACTIVE FILTERS; ELECTRIC EQUIPMENT; INSULATED GATE BIPOLAR TRANSISTORS (IGBT); OPTIMIZATION; PHOTOLITHOGRAPHY;

POWER ELECTRONICS;

EID: 72949090388     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A. Icaza, G. Wachutka, F. Hirler, J. Krumrey, R. Henninger: Failure of multiple-cell power DMOS transistors in avalanche operation, Proceedings ESSDERC, Estoril, Portugal, 2003
2. R. Stengl, U. Gösele, C. Fellinger, M. Beyer, S. Walesch: Variation of lateral doping as a field terminator for high-voltage power devices, IEEE Trans. On Electron Devices, vol. 33, no.3, pp. 426-428, 1986
3. DESSIS TCAD, distributed by Synopsys, Inc.
4. U. Knipper, F. Pfirsch, T. Raker, J. Niedermeyr, G. Wachutka: Time-periodic avalanche-breakdown at the edge termination of power devices, Proceedings ISPSD, Orlando, USA, 2008
5. A. Icaza Deckelmann, G. Wachutka, F. Hirler, J. Krumrey: UIS-failure for DMOS power transistors, Proceedings ESSDERC, Bologna, Italy, 2000