Towards hardware implementation of bzip2 data compression algorithm

Proceedings of the 16th International Conference - Mixed Design of Integrated Circuits and Systems, MIXDES 2009

Volumn , Issue , 2009, Pages 337-340

  Szecówka, Przemyslaw M ^a   Mandrysz, Tomasz ^a  

^a WROCLAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

Burrows Wheeler transform; Bzip2; Data compression; FPGA; Hardware; Huffman coding; VHDL

Indexed keywords

BITONIC SORT; BURROWS-WHEELER TRANSFORM; BZIP2; CRITICAL PARTS; DATA BLOCKS; DATA COMPRESSION ALGORITHMS; DIGITAL ARCHITECTURE; FINITE STATE MACHINES; HARDWARE IMPLEMENTATIONS; HUFFMAN CODING; MOVE-TO-FRONT;

COMPUTER HARDWARE DESCRIPTION LANGUAGES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INTEGRATED CIRCUITS; LOGIC DEVICES;

DATA COMPRESSION;

EID: 72149099313     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. J. Seward, "A program and library for data compression. Bzip2 and libbzip2", version 1.0.5, (www.bzip.org), .2008.
2. B. S. Pimentel, J. H de Avila and R. L. Campos, "A FPGA Implementation of a DCT-Based Digital Electrocardiographic Signal Compression Device", Integrated Circuits and Systems Design, 2001, 44 - 49.
3. Y. Yongming, L. Jungang and W. Jianmin, "LADAT Arithmetic Improved and Hardware Implemented for FPGA - Based ECG Data Compression", Second IEEE Conference on Industrial Electronics and Applications, 2007.
4. Xilinx Spartan-3 Family Complete Data Sheet, (www.xilinx.com), Xilinx Inc. 2007.
5. M. F. Ionescu and K. E. Schauser, "Optimizing Parallel Bitonic Sort", Parallel Processing Symposium, 1997, 303 - 309.
6. IEEE Standard, VHDL Language Reference Manual, (IEEE Std 1076), 2000 Edition.