3D interconnects for dense die stack packages

2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Volumn , Issue , 2009, Pages

  Mirkarimi, L ^a   Huynh, M ^a   Savalia, P ^a   Oganesian, V ^a  

^a Tessera Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTERCONNECTS; 3D INTERCONNECT; DIE STACK; ENVIRONMENTAL STRESS; PACKAGE TECHNOLOGIES; WAFER LEVEL;

PACKAGING;

THREE DIMENSIONAL;

EID: 70549099888     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2009.5306574     Document Type: Conference Paper

References (4)

1. M. Healy and S.K. Lim, "A study of stacking limit and scalability in 3D ICs: an interconnect perspective", ECTC, June 2009.
2. M. Robinson and J. Leal, "Conformal polymer edge interconnect method for high capacity", and performance in solid state storage Applications", ECTC, June 2009.
3. C. Val, P. Couderc, N. Boulay "Stacking technique of known rebuilt wafers without through silicon via", EPTC, Singapore, Dec. 2008.
4. P. Savalia, I. Mohammed and L. Mirkarimi, Structural design aspects for reliability of high-density chip-scale packages using a wafer-stack process", IMAPS 2009.