Fabrication and packaging of microbump interconnections for 3D TSV

2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Volumn , Issue , 2009, Pages

  Yoon, Seung Wook ^a   Ku, Jae Hoon ^a   Suthiwongsunthorn, Nathapong ^a   Marimuthu, Pandi Chelvam ^a   Carson, Flynn ^b  

^a STATS CHIPPAC LTD   (Singapore)

^b STATS ChipPAC Ltd   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3D STACKING TECHNOLOGY; BONDING CONDITIONS; CHIP STACKING; FINE PITCH; FLIP-CHIP BONDERS; FLIP-CHIP INTERCONNECTION; HIGH DENSITY; MECHANICAL CHARACTERIZATIONS; MEMORY BANDWIDTHS; METAL LAYER; MICRO-BUMPS; PACKAGE TECHNOLOGIES; PERFORMANCE SIGNALS; POWER CONNECTIONS; PROCESSOR PERFORMANCE; RELIABILITY TEST; SI CHIPS; SILICON DIE; THERMO-COMPRESSION; THROUGH-SILICON-VIA; ULTRA FINE PITCH; UNDER-BUMP METALLURGIES; UNDERFILL PROCESS; UNDERFILLING; VOID-FREE; WIRING DENSITY;

BONDING; CHIP SCALE PACKAGES; COMPUTER SCIENCE; SILICON; SILICON WAFERS; TECHNOLOGY; THREE DIMENSIONAL;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 70549089936     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2009.5306554     Document Type: Conference Paper

References (4)

1. Seung Wook Yoon, "3D integration with TSV technology," Invited talk in 3D TSV technology session, SEMICON Singapore, May 5-7, 2008
2. Hu G., Kalyanam H., Krishnamoorthy and Polka L., "Package Technology to Address the Memory Bandwidth Challenge for Tera-scale Computing," IntelTechnology Journal, Vol. 11, No. 3 (2007), pp. 197-206.
3. Knickerbocker, J. U. et al, "Development of next generation systemon-acage (SOP) technology based on silicon carriers with fine-pitch interconnection," IBM J. Res. Dev. Vol. 49, No. 4/5 (2005), pp. 725-754.
4. th Electronic Packaging Technology Conference 2008, 11-14 Dec 2008, Singapore