A fault tolerant, area efficient architecture for shor's factoring algorithm

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2009, Pages 383-394

  Whitney, Mark G ^a   Isailovic, Nemanja ^a   Patel, Yatish ^a   Kubiatowicz, John ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

CAD; Control; Ion trap; Layout; Quantum computing

Indexed keywords

ADDER CIRCUIT; ANCILLA; AREA EFFICIENT; CAD FLOW; CARRY LOOKAHEAD ADDER; DELAY PRODUCT; FAULT-TOLERANT; ION TRAP; ION TRAPS; ORDER OF MAGNITUDE; PHYSICAL COMPONENTS; QUANTUM CIRCUIT; QUANTUM COMPUTING; RIPPLE CARRY ADDERS; SHOR'S FACTORING ALGORITHM;

ADDERS; ERROR CORRECTION; FAULT TOLERANCE; FLOW SIMULATION; OPTIMIZATION; QUALITY ASSURANCE; QUANTUM COMPUTERS; QUANTUM OPTICS; QUANTUM THEORY;

COMPUTER ARCHITECTURE;

EID: 70450280916     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1555754.1555802     Document Type: Conference Paper

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