An events based algorithm for distributing concurrent tasks on multi-core architectures

Computer Physics Communications

Volumn 181, Issue 2, 2010, Pages 341-354

  Holmes, David W ^a   Williams, John R ^a   Tilke, Peter ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b SCHLUMBERGER DOLL RESEARCH   (United States)

Author keywords

H Dispatch; Multi core; Numerical simulation; Port based programming

Indexed keywords

COMPUTATIONAL TASK; CONCURRENT TASKS; CORE MACHINES; DISPATCH ALGORITHMS; FINITE DIFFERENCE; GARBAGE COLLECTION; HETEROGENEOUS ARCHITECTURES; ITERATION ALGORITHMS; LINEAR SPEED-UP; MEMORY MANAGEMENT; MEMORY RESOURCES; MULTI CORE; MULTICORE ARCHITECTURES; MULTIPLE THREADS; NUMERICAL SIMULATION; PARALLEL PERFORMANCE; PROGRAMMING MODELS; SHARED MEMORY ARCHITECTURE; SPATIAL DECOMPOSITIONS; SPEED-UPS; TASK MANAGEMENT; TIME-STEPPING;

ALGORITHMS; MATHEMATICAL MODELS; MESSAGE PASSING; PROGRAM PROCESSORS; REFUSE COLLECTION; SIMULATORS; WASTE DISPOSAL;

COMPUTATIONAL EFFICIENCY;

EID: 70450223892     PISSN: 00104655     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.cpc.2009.10.009     Document Type: Article

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