A multi-FPGA architecture for stochastic Restricted Boltzmann Machines

FPL 09: 19th International Conference on Field Programmable Logic and Applications

Volumn , Issue , 2009, Pages 168-173

  Ly, Daniel L ^a   Chow, Paul ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

C PROGRAMS; COMPUTATIONAL SPEED; FPGA ARCHITECTURES; HIGH-PRECISION; INTEL PROCESSORS; LOOK UP TABLE; MULTI-FPGA; PARTITIONING ALGORITHMS; PIECEWISE LINEAR; RESTRICTED BOLTZMANN MACHINE; SIGMOID FUNCTION; SPEED-UPS; STOCHASTIC NODES;

AXIAL FLOW; COMPUTATIONAL EFFICIENCY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUNCTION GENERATORS; PIECEWISE LINEAR TECHNIQUES; PROGRAM PROCESSORS; STOCHASTIC SYSTEMS;

NEURAL NETWORKS;

EID: 70450015220     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2009.5272516     Document Type: Conference Paper

References (7)

1. Y. Freund and D. Haussler, "Unsupervised Learning of Distributions on Binary Vectors Using Two Layer Networks," Neural Information Processing Systems Conference (NIPS) , pp. 912-919, 1992.
2. D. Ly and P. Chow, "A High-Per formance FPGA Architectu re for Restricted Boltzmann Machines," ACM International Symposium on FPGAs, pp. 73-82, 2009.
3. M. Tommiska, "Efficient digita l implementation of the sigmoid function for reprogrammable logic," lEE Proceedings - Computers and Digital Techniques, pp. 403-411 , 2003.
4. A. Savich, M. Moussa, and S. Areibi, "The Impact of Arithemetic Representation on Implementing MLP-BP on FPGAs: A Study," IEEE Transactions on Neural Networks, vol. 18, no. I, pp. 240-252, 2007.
5. B. Bharkhada, J. Hauser, and C. Purdy, "Efficient FPGA implementation of a generic function approximator and its application to neural net computation ," IEEE International Symposium on Micro- NanoMechatronics and Human Science, pp. 843-846, 2003.
6. P. L' Ecuyer, "Maximally Equidistributed Combined Tausworthe Generators ," Mathematics ofComputation, vol. 65, no. 213, pp. 203-213, 1996.
7. Y. Liao, "Neural Networks in Hardware: A Survey," Santa Cruz, CA, USA, Tech. Rep., 2001. [8] C. Chang, J. Wawrzynek, and R. Brodersen, "BEE2: A High-End Reconfigurable Computing System," IEEE Design & Test of Computers, pp. 114-125 , 2005.