Process variation characterization of chip-level multiprocessors

Proceedings - Design Automation Conference

Volumn , Issue , 2009, Pages 694-697

  Lide, Zhang ^a   Bai, Lan S ^b   Dick, Robert P ^a   Li, Shang ^c   Joseph, Russ ^a  

^a NORTHWESTERN UNIVERSITY   (United States)

^b University of Michigan   (United States)

^c UNIVERSITY OF COLORADO   (United States)

Author keywords

Characterization; Process variation; Software

Indexed keywords

ADAPTATION TECHNIQUES; ADDITIONAL COSTS; AGING EFFECTS; CHIP-LEVEL; CMP PROCESS; CONTROL TECHNIQUES; IMPROVING SYSTEMS; LEAKAGE POWER CONSUMPTION; MULTIPROCESSOR SYSTEMS ON CHIPS; ONLINE TECHNIQUE; OPERATING SYSTEMS; POWER CONSUMPTION; POWER MANAGEMENTS; PROCESS VARIATION; REAL PROCESSORS; SOFTWARE; STATIC MAP; TASK ASSIGNMENT; TESTING PROCESS; WITHIN-DIE VARIATIONS;

ACCESS CONTROL; COMPUTER AIDED DESIGN; COMPUTER OPERATING SYSTEMS; DIES; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; ENERGY MANAGEMENT; FAULT TOLERANCE; MICROPROCESSOR CHIPS; QUALITY ASSURANCE; SCHEDULING ALGORITHMS; TEMPERATURE MEASUREMENT;

MULTIPROCESSING SYSTEMS;

EID: 70350741517     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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