Study of nanoimprint applications toward 22nm node CMOS devices

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6921, Issue , 2008, Pages

  Yoneda, Ikuo ^a   Mikami, Shinji ^a   Ota, Takumi ^a   Koshiba, Takeshi ^a   Ito, Masamitsu ^a   Nakasugi, Tetsuro ^a   Higashiki, Tatsuhiko ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

CMOS devices; Nanoimprint lithography; S FIL; Template

Indexed keywords

CD UNIFORMITY; CMOS DEVICES; MOLECULAR IMPRINT; MULTILAYER RESISTS; NANO-IMPRINT; NANOIMPRINT APPLICATIONS; PATTERN DENSITY; S-FIL; SPREAD-TIME; STEP AND FLASH IMPRINT LITHOGRAPHY; TEMPLATE; TEST DEVICE; UNIT PROCESS;

DEFECT DENSITY; DEFECTS; EQUIPMENT; FABRICATION; TESTING;

NANOIMPRINT LITHOGRAPHY;

EID: 70350680748     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.771149     Document Type: Conference Paper

References (4)

1. T. Bailey, B. J. Choi, M. Colburn, M. Meissl, S. Shaya, J. G. Ekerdt, S. V. Sreenivasan, and C. G. Willson, J. Vac. Sci. Technol. B 18(6), 3572 (2000).
2. Gerard M. Schmid, Ecron Thompson, Nick Stacy, Douglas J. Resnick, Deirdre L. Olynick, Erick H. Anderson, Proc. SPIE vol.6517-42 (2007).
3. J. Perez, K. Selinidis, S. Johnson, B. Fletcher, F. Xu, J. Maltabes, I. McMackin, D. Resnick, S. V. Sreenivasan, Proc. SPIE vol.6517-20 (2007).
4. Mark Melliar-Smith, SPIE Advanced Lithography 2007.