Blind optimization for exploiting hardware features

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 5501 LNCS, Issue , 2009, Pages 251-265

  Knights, Dan ^a   Mytkowicz, Todd ^a   Sweeney, Peter F ^a   Mozer, Michael C ^a   Diwan, Amer ^a  

^a UCB 450   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK SUITES; DATA LAYOUTS; HARDWARE FEATURES; HARDWARE MANUFACTURERS; HARDWARE STRUCTURES; OPTIMIZATION APPROACH; OPTIMIZATION STRATEGY; OPTIMIZING COMPILERS; SIMPLIFIED MODELS; SOFTWARE SYSTEMS;

COMPUTER SOFTWARE; HARDWARE; MICROPROCESSOR CHIPS; PROGRAM COMPILERS;

OPTIMIZATION;

EID: 70350663151     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-00722-4_18     Document Type: Conference Paper

References (24)

1. Arnold, M., Fink, S., Grove, D., Hind, M., Sweeney, P.F.: Adaptive optimization in the Jalape-no JVM. ACM SIGPLAN Notices 35(10), 47-65 (2000)
2. Arnold, M., Hind, M., Ryder, B.G.: Online feedback-directed optimization of java. SIGPLAN Not. 37(11), 111-129 (2002)
3. Browne, S., Dongarra, J., Garner, N., London, K., Mucci, P.: A scalable crossplatform infrastructure for application performance tuning using hardware counters. In: SC, Dallas, Texas (November 2000)
4. Calder, B., Grunwald, D.: Reducing branch costs via branch alignment. In: ASPLOS (October 1994)
5. Cavazos, J., Moss, J.E.B.: Inducing heuristics to decide whether to schedule. In: PLDI, pp. 183-194. ACM Press, New York (2004)
6. Cavazos, J., O'Boyle, M.F.P.: Automatic tuning of inlining heuristics. In: SC, Washington, DC, USA, p. 14. IEEE Computer Society, Los Alamitos (2005)
7. Cooper, K.D., Subramanian, D., Torczon, L.: Adaptive optimizing compilers for the 21st century. J. Supercomput. 23(1), 7-22 (2002)
8. Gloy, N., Blackwell, T., Smith, M.D., Calder, B.: Procedure placement using temporal ordering information. In: MICRO, pp. 303-313 (1997)
9. Hashemi, A.H., Kaeli, D.R., Calder, B.: Efficient procedure mapping using cache line coloring. In: PLDI, pp. 171-182 (1997)
10. Hauswirth, M.,Sweeney,P.F., Diwan, A., Hind, M.: Vertical profiling: Understanding the behavior of object-oriented applications. In: OOPSLA (2004)
11. Jiménez, D.A.: Code placement for improving dynamic branch prediction accuracy. In: PLDI, pp. 107-116. ACM Press, New York (2005)
12. Lau, J., Arnold, M., Hind, M., Calder, B.: Online performance auditing: using hot optimizations without getting burned. SIGPLAN Not. 41(6), 239-251 (2006)
13. Lee, H., von Dincklage, D., Diwan, A., Eliot, J., Moss, B.: Understanding the behavior of compiler optimizations. Softw. Pract. Exper. 36(8), 835-844 (2006)
14. Massalin, H.: Superoptimizer: a look at the smallest program. SIGPLAN Not. 22(10), 122-126 (1987)
15. Mcfarling, S.: Program optimization for instruction caches. In: ASPLOS, pp. 183-191. ACM, New York (1989)
16. Mcfarling, S.: Procedure merging with instruction caches. In: PLDI, pp. 71-79 (1991)
17. McGovern, A., Moss, E., Barto, A.G.: Building a basic block instruction scheduler with reinforcement learning and rollouts. Mach. Learn. 49(2-3), 141-160 (2002)
18. Mytkowicz, T., Diwan, A., Hauswirth, M., Sweeney, P.F.: Producing wrong data without doing anything obviously wrong? In: ASPLOS (2009)
19. Pan, Z., Eigenmann, R.: Fast and effective orchestration of compiler optimizations for automatic performance tuning. In: CGO, Washington, DC, USA, pp. 319-332. IEEE Computer Society, Los Alamitos (2006)
20. Pettis, K., Hansen, R.C.: Profile guided code positioning. In: PLDI, pp. 16-27 (June 1990)
21. Singer, J., Brown, G., Watson, I., Cavazos, J.: Intelligent selection of applicationspecific garbage collectors. In: ISMM, pp. 91-102. ACM Press, New York (2007)
22. Standard Performance Evaluation Corporation. SPEC CPU2006 Benchmarks, http://www.spec.org/cpu2006/
23. Tomiyama, H., Yasuura, H.: Code placement techniques for cache miss rate reduction. ACM Trans. Des. Autom. Electron. Syst. 2(4), 410-429 (1997)
24. Triantafyllis, S., Vachharajani, M., Vachharajani, N., August, D.I.: Compiler optimization-space exploration. In: CGO, Washington, DC, USA, pp. 204-215. IEEE Computer Society Press, Los Alamitos (2003)