On-chip PVT compensation techniques for low-voltage CMOS digital LSIs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2009, Pages 1565-1568

  Tsugita, Yusuke ^a   Ueno, Ken ^a   Asai, Tetsuya ^a   Amemiya, Yoshihito ^a   Hirose, Tetsuya ^b  

^a HOKKAIDO UNIVERSITY   (Japan)

^b KOBE UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT PERFORMANCE; CMOS DIGITAL CIRCUITS; COMPENSATION TECHNIQUES; DEVICE MISMATCH; DIGITAL LSI; LOW-VOLTAGE; MONTE CARLO SIMULATION; MOSFETS; ON CHIPS; ON-CHIP PROCESS; PERFORMANCE IMPROVEMENTS; PVT VARIATIONS; REFERENCE CURRENTS; SATURATION CURRENT; SPICE SIMULATIONS; STANDARD CMOS; SUPPLY VOLTAGES;

COMPUTER SIMULATION; DEGRADATION; DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; MONTE CARLO METHODS;

SPICE;

EID: 70350160113     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2009.5118068     Document Type: Conference Paper

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