Scaling trends of the AES S-Box low power consumption in 130 and 65 nm CMOS technology nodes

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2009, Pages 1385-1388

  Kamel, Dina ^a   Standaert, François Xavier ^a   Flandre, Denis ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

65-NM NODE; 65NM CMOS TECHNOLOGY; ADVANCED ENCRYPTION STANDARD; LOW POWER; LOW-POWER CONSUMPTION; ORDER OF MAGNITUDE; POWER BUDGETS; POWER CONSUMPTION; RADIO FREQUENCY IDENTIFICATION DEVICES; S-BOXES; SCALING TRENDS; SCHEMATIC SIMULATION; SUPPLY VOLTAGES;

CMOS INTEGRATED CIRCUITS; CRYPTOGRAPHY; NETWORK SECURITY; RADIO FREQUENCY IDENTIFICATION (RFID);

ELECTRIC POWER UTILIZATION;

EID: 70350139339     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2009.5118023     Document Type: Conference Paper

References (11)

1. D. Bol, R. Ambroise, D. Flandre and J.-D. Legat, "Interests and limitations of technology scaling for subthreshold logic", in IEEE Trans. on VLSI Systems, in press, 12 p., 2009.
2. M. Feldhofer, S. Dominikus, and J.Wolkerstorfer, "Strong authentication for RFID systems using the AES algorithm," Proceedings of CHES 2004, LNCS 3156, pp 357-370, Boston, USA, August 2004.
3. Y M. Feldhofer, J. Wolkerstorfer, and V. Rijmen, "AES implementation on a grain of sand," IEE Proceedings in Information Security, pp 13-20, 2005.
4. P. Hamalainen, T. Alho, M. Hannikainen, and T. D. Hamalainen, "Design and implementation of Low-Area and Low-Power AES encryption hardware core," in 9th Euromicro Conference on Digital System Design (DSD 2006), pp 577-583, 2006.
5. M. Hutter, "Embedding Crypto on Low-Cost RFID Tags," in Talk given at Praxistag RFID-Sicherheit, Oberhausen, Deutschland, December 2007.
6. ITRS Process Integration, "'Devices & Structures,'" in International Technology Roadmap for Semiconductors , 2007 eddition.
7. J.-P. Kaps, "Cryptography for Ultra-Low Power Devices", in PhD Dissertation, Worcester Polytechnic Institute, May 2006.
8. A. S. W. Man, E. S. Zhang, V. K. N. Lau, C. Y. Tsui, and H. C. Luong, "Low Power VLSI design for a RFID passive tag baseband system enhanced with an AES cryptography engine," in RFID Eurasia, pp 1-6, 2007.
9. N. Mentens, L. Batina, B. Preneel, and I. Verbauwhede, "A systematic evaluation of compact hardware implementations for the Rijndael SBOX," Proceedings of CT-RSA 2005, Lecture Notes in Computer Science, vol 3376 pp 323-333, 2005.
10. A. Satoh, S. Morioka, K. Takano, and S. Munetoh, "A compact Rijndael hardware architecture with S-box optimization," Proceedings of ASIACRYPT 2001, Lecture Notes in Computer Science, vol 2248, pp 239-254, 2001.
11. J. Wolkerstorfer, E. Oswald and M. Lamberger, "An ASIC implementation of the AES Sboxes," Proceedings of CT-RSA 2002, Lecture Notes in Computer Science, vol 2271, pp 67-78, 2002.