Dealing with AADL end-to-end flow latency with UML MARTE

Proceedings of the IEEE International Conference on Engineering of Complex Computer Systems, ICECCS

Volumn , Issue , 2008, Pages 228-233

  Lee, Su Young ^a   Mallet, Frédéric ^a   De Simone, Robert ^a  

^a INPIA Sophia Antipolis   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DATA TRANSFER; EMBEDDED SYSTEMS; REAL TIME SYSTEMS;

APERIODIC TASKS COMMUNICATION; TIME MODEL FACILITIES;

UNIFIED MODELING LANGUAGE;

EID: 44149124559     PISSN: 27708527     EISSN: 27708535     Source Type: Conference Proceeding    
DOI: 10.1109/ICECCS.2008.14     Document Type: Conference Paper

References (8)

1. SAE: Architecture Analysis and Design Language (AADL). June 2006, document AS5506/1. http://www.sae.org/technical/standards/AS5506/1.
2. OMG: UML profile for Modeling and Analysis of RealTime and Embedded systems (MARTE), beta 1, August 2007, document ptc/07-08-04.
3. André C, Mallet F, de Simone R (2007): Modeling Time(s). Springer LNCS 4735:559-573.
4. Feiler P.H, Hansson J: Flow Latency Analysis with the Architecture Analysis and Design Language (AADL). Carnegie Mellon University, Technical Note CMU/SEI-2007-TN-010, June 2007.
5. Faugère M, Bourbeau T, de Simone R, Gérard S (2007): MARTE: Also an UML Profile for Modeling AADL Applications. ICECCS:359-364.
6. Lee E.A, Sangiovanni-Vincentelli A.L (1998): A framework for comparing models of computation. IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, 17(12):1217-1229.
7. OSATE release 1.5.3. http://www.aadl.info
8. André C, Mallet F, de Simone R (2007): Modeling of Immediate vs. Delayed Data Communications: from AADL to UML MARTE. ECSI FDL 2007.