Fault insertion testing of a novel CPLD-based fail-safe system

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 214-219

  Grießnig, Gerhard ^a   Mader, Roland ^b   Steger, Christian ^b   Weiß, Reinhold ^b  

^a AVL LIST GMBH   (Austria)

^b GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

CPLD; Fail safe system; Fault injection; Fault insertion testing; IEC 61508; Safety integrity; VHDL

Indexed keywords

CPLD; FAIL-SAFE SYSTEM; FAULT INJECTION; FAULT INSERTION TESTING; IEC 61508; SAFETY INTEGRITY; VHDL;

COMPUTER HARDWARE DESCRIPTION LANGUAGES; DIGITAL TO ANALOG CONVERSION; LOGIC DEVICES; MICROCONTROLLERS; QUALITY ASSURANCE; SOFTWARE TESTING;

SAFETY TESTING;

EID: 70350062097     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. P. Sundaram, and J.G. D'Ambrosio, "Controller integrity in automotive failsafe system architectures," SAE Transactions, 2006, vol. 115, pp. 370-377.
2. M. Abramovici, A.D. Friedman, and M.A. Breuer, Digital Systems Testing and Testable Design. IEEE PRESS. 1994.
3. W.L. Gallagher, H.H. Yao, and E.E. Swartzlander Jr., "Fault simulation with PLDs," In Proc. of the 31st Asilomar Conference on Signals, Systems & Computers, 1997, pp. 411-415.
4. Shih-Arn Hwang, Jin-Hua Hong, and Cheng-Wen Wu, "Sequential circuit fault simulation using logic emulation," IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems, 1998, vol 17, pp. 724-736.
5. P. Ellervee, J. Raik, K. Tammemäe, and R. Ubar, "Environment for FPGA-based fault emulation," In Proc. of the Estonian Academy of Sciences. Engineering, 2006, vol 12, pp. 323-335.
6. IEC 61508, Functional safety of electrical/electronic/programmable electronic safety-related systems.
7. J. Gracia, J.C. Baraza, D. Gil, and P.J. Gil, "Comparison and. application of different VHDL-based fault injection techniques," In Proc. of the International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'01), 2001, pp. 233-241.
8. E. Jenn, J. Arlat, M. Rimen, J. Ohlsson, and J. Karlsson, "Fault injection into VHDL models: the MEFISTO tool.," In Proc. of the 24th International Symposium on Fault-Tolerant Computing (FTCS-24), 1994, pp. 66-75.
9. P. Leventis, B. Vest, M. Hutton, and D. Lewis, "MAX II: A low-cost, high-performance LUT-based CPLD," In Proc. of the Custom Integrated Circuits Conference, 2004, pp. 443-446.
10. G. Grießnig, C. Steger, and R. Weiß, "CPLD basierende homogen redundante fehlersichere Architektur," In Proc. of the Informationstagung Mikroelektronik (ME08), 2008, pp. 201-205.