Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storage

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 454-459

  Xu, Guo ^a   Schaumont, Patrick ^a  

^a Virginia Polytechnic Institute and State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE SPEED; CO-PROCESSORS; COMMUNICATION LINKS; COMPUTATIONAL ASPECTS; CONTROL HIERARCHY; DESIGN SPACE EXPLORATION; DISTRIBUTED STORAGE; ECC SYSTEM; ELLIPTIC CURVE CRYPTOGRAPHY; FPGA TECHNOLOGY; HARDWARE/SOFTWARE CO-DESIGN; LOCAL CONTROL; OPTIMAL CHOICE; PRODUCT IMPROVEMENT; PROTOTYPE IMPLEMENTATIONS; SOC ARCHITECTURE; SOC DESIGNS; SYSTEM CONFIGURATIONS; SYSTEM INTEGRATION; SYSTEM LEVELS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MICROPROCESSOR CHIPS; OPTIMIZATION; PROGRAMMABLE LOGIC CONTROLLERS; SOFTWARE PROTOTYPING; SPACE RESEARCH;

DESIGN;

EID: 70350059460     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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