A low-power bit-serial multiplier for finite fields GF(2/sup m/)

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 37-40

  Grossschadl, Johnitit ^a  

^a GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

bit serial multiplier architecture; Finite field arithmetic; low power VLSI design; smart card crypto coprocessor

Indexed keywords

ARITHMETIC CIRCUIT; BINARY FIELDS; BINARY FINITE FIELDS; BIT-SERIAL ARCHITECTURE; BIT-SERIAL MULTIPLIERS; FINITE FIELD ARITHMETIC; POLYNOMIAL BASIS; VLSI DESIGN;

SMART CARDS;

EID: 33750822634     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922163     Document Type: Conference Paper

References (7)

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