Proximity communication flip-chip package with micron chip-to-chip alignment tolerances

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2009, Pages 966-971

  Sze, T ^a   Giere, M ^a   Guenin, B ^a   Nettleton, N ^a   Popovic, D ^a   Shi, J ^a   Bezuk, S ^a,b   Ho, R ^a   Drost, R ^a   Douglas, D ^a  

^a SUN MICROSYSTEMS   (United States)

^b QUALCOMM INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITIVE COUPLINGS; CHIP ALIGNMENT; FLIP-CHIP PACKAGES; HETEROGENEOUS INTEGRATION; PACKAGING TECHNIQUES; PERFORMANCE GAIN; PROCESS TECHNOLOGIES; PROCESSOR CHIPS; PROXIMITY COMMUNICATION; SILICON DIE; STANDARD CMOS TECHNOLOGY; SYSTEM LEVELS;

CMOS INTEGRATED CIRCUITS; FLASH MEMORY; HUMAN COMPUTER INTERACTION; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; TECHNOLOGY;

CHIP SCALE PACKAGES;

EID: 70349655260     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2009.5074130     Document Type: Conference Paper

References (3)

1. Sun Internal document, to be published.
2. Chow, A.; Hopkins, D.; Ron Ho; Drost, R, "Measuring 6D Chip Alignment in Multi-Chip Packages, " Sensors, 2007 IEEE, 28-31 Oct. 2007 Page(s): 1307 - 1310.
3. Hopkins, D., ISSCC 2007.